CONTENTS
Preface
Acknowledgments
PART I BASIC DIGITAL CIRCUITS
1 Gate-level combinational circuit
1.1 Introduction
1.2 General description
1.3 Structural description
1.4 Testbench
1.5 Bibliographic notes
1.6 Suggested experiments
2 Overview of FPGA and EDA software
2.1 Introduction
2.2 FPGA
2.3 Overview of the Digilent S3 board
2.4 Development flow
2.5 Overview of the Xilinx ISE project navigator
2.6 Short tutorial on ISE project navigator
2.7 Short tutorial on the ModelSim HDL simulator
2.8 Bibliographic notes
2.9 Suggested experiments
3 RT-Ievel combinational circuit
3.1 Introduction
3.2 RT-level components
3.3 Routing circuit with concurrent assignment statements
3.4 Modeling with a process
3.5 Routing circuit with if and case statements
3.6 Constants and generics
3.7 Design examples
3.8 Bibliographic notes
3.9 Suggested experiments
4 Regular Sequential Circuit
4.1 Introduction
4.2 HDL code of the FF and register
4.3 Simple design examples
4.4 Testbench for sequential circuits
4.5 Case study
4.6 Bibliographic notes
4.7 Suggested experiments
5 FSM
5.1 Introduction
5.2 FSM code development
5.3 Design examples
5.4 Bibliographic notes
5.5 Suggested experiments
6 FSMD
6.1 Introduction
6.2 Code development of an FSMD
6.3 Design examples
6.4 Bibliographic notes
6.5 Suggested experiments
PART II I/O MODULES
7 UART
7.1 Introduction
7.2 DART receiving subsystem
7.3 DART transmitting subsystem
7.4 Overall DART system
7.5 Customizing a DART
7.6 Bibliographic notes
7.7 Suggested experiments
8 PS2 Keyboard
8.1 Introduction
8.2 PS2 receiving subsystem
8.3 PS2 keyboard scan code
8.4 PS2 keyboard interface circuit
8.5 Bibliographic notes
8.6 Suggested experiments
9 PS2 Mouse
9.1 Introduction
9.2 PS2 mouse protocol
9.3 PS2 transmitting subsystem
9.4 Bidirectional PS2 interface
9.5 PS2 mouse interface
9.6 Bibliographic notes
9.7 Suggested experiments
10 External SRAM
10.1 Introduction
10.2 Specification of the IS61LV25616AL SRAM
10.3 Basic memory controller
10.4 A safe design
10.5 More aggressive design
10.6 Bibliographic notes
10.7 Suggested experiments
11 Xilinx Spartan-3 Specific Memory
11.1 Introduction
11.2 Embedded memory of Spartan-3 device
11.3 Method to incorporate memory modules
11.4 HDL templates for memory inference
11.5 Bibliographic notes
11.6 Suggested experiments
12 VGA controller I: graphic
12.1 Introduction
12.2 VGA synchronization
12.3 Overview of the pixel generation circuit
12.4 Graphic generation with an object-mapped scheme
12.5 Graphic generation with a bit-mapped scheme
12.6 Bibliographic notes
12.7 Suggested experiments
13 VGA controller II: text
13.1 Introduction
13.2 Text generation
13.3 Full-screen text display
13.4 The complete pong game
13.5 Bibliographic notes
13.6 Suggested experiments
PART III PICOBLAZE MICROCONTROLLER XILINX SPECIFIC
14 PicoBlaze Overview
14.1 Introduction
14.2 Customized hardware and customized software
14.3 Overview of PicoBlaze
14.4 Development flow
14.5 Instruction set
14.6 Assembler directives
14.7 Bibliographic notes
15 PicoBlaze Assembly Code Development
15.1 Introduction
15.2 Useful code segments
15.3 Subroutine development
15.4 Program development
15.5 Processing of the assembly code
15.6 Syntheses with PicoBlaze
15.7 Bibliographic notes
15.8 Suggested experiments
16 PicoBlaze I/O Interface
16.1 Introduction
16.2 Output port
16.3 Input port
16.4 Square program with a switch and seven-segment LED display interface
16.5 Square program with a combinational multiplier and DART console
16.6 Bibliographic notes
16.7 Suggested experiments
17 PicoBlaze Interrupt Interface
17.1 Introduction
17.2 Interrupt handling in PicoBlaze
17.3 External interface
17.4 Software development considerations
17.5 Design example
17.6 Bibliographic notes
17.7 Suggested experiments
Appendix A: Sample VHDL templates
A.l General VHDL constructs
A.2 Combinational circuits
A.3 Memory Components
A.4 Regular sequential circuits
A.5 FSM
A.6 FSMD
A.7 S3 board constraint file (83. lief)
References
Topic Index
Copyright © 2008 by John Wiley & Sons, Inc. All rights reserved.
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Library of Congress Cataloging-in-Publication Data:
Chu, Pong P., 1959–
FPGA prototyping by VHDL examples/Pong P. Chu.
p.cm.
Includes bibliographical references and index.
ISBN 978-0-470-18531-5 (cloth: alk. paper)
1. Field programmable gate arrays-Design and construction. 2. Prototypes, Engineering. 3.VHDL (Computer hardware description language) I. Title.
TK7895.G36C485 2008
621.39’5-dc22
2007029063
To my parents, Chia-Chi and Chi-Te, my wife, Lee, and my daughter, Patricia
PREFACE
HDL (hardware description language) and FPGA (field-programmable gate array) devices allow designers to quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify operation of the physical implementation. As these technologies mature, they have become mainstream practice. We can now use a PC and an inexpensive FPGA prototyping board to construct a complex and sophisticated digital system. This book uses a “learning by doing” approach and illustrates the FPGA and HDL development and design process by a series of examples. A wide range of examples is included, from a simple gate-level circuit to an embedded system with an 8-bit soft-core microcontroller and customized I/O peripherals. All examples can be synthesized and physically tested on a prototyping board.
Focus and audience
Focus The main focus of this book is on the effective derivation of hardware, not the syntax of HDL. Instead of explaining every language construct, the book is limited to a small synthesizable subset and uses about a dozen code templates to provide the skeletons of various types of circuits. These templates are general and can easily be integrated to construct a large, complex system. Although this approach limits the “freedom” of syntactic expression, it will not prevent us from developing innovative hardware architecture. Because of the generality and flexibility of HDL, the same circuit can usually be described by a wide variety of language constructs and coding styles. Many of these codes are intended for modeling. They may lead to unnecessarily complex hardware implementation and sometimes cannot be synthesized at all. The template approach actually forces us to think more about hardware and develop a good coding practice for synthesis. Since we are more interested in hardware, it is more beneficial to spend time on developing 10 different hardware architectures with the same code template rather than describing the same circuit with 10 different versions of codes.
There are two popular HDLs, VHDL and Verilog. Both languages are used widely and are IEEE standards. This book uses VHDL, and a separate book with a similar title uses Verilog. Despite the drastic syntactic differences in the two languages, their capabilities are very similar, particularly for our purposes. After we comprehend the design practice and coding methodology in one language, learning the other language is rather straightforward.
Although the book is intended for beginning designers, the examples follow strict design guidelines and prepare readers for future endeavors. The coding and design practice is “forward compatible,” which means that:
In summary, the book is a hands-on, hardware-centric text that involves minimal HDL overhead and follows good design and coding practice to achieve maximal forward comparability.
Audience and perquisites The book contains three major parts: basic digital circuits, peripheral modules, and embedded microcontroller. The intended audience is students in an introductory or advanced digital system design course as well as practicing engineers who wish to learn FPGA-and HDL-based development. For the materials in the first two parts, readers need to have a basic knowledge of digital systems, usually a required course in electrical engineering and computer engineering curricula. For the materials in the third part, prior exposure to assembly language programming will be helpful.
Logistics
Although a major goal of this book is to teach readers to develop software-independent and device-neutral HDL codes, we have to choose a software package and a prototyping board to synthesize and implement the design examples. The synthesis software and FPGA devices from Xilinx, a leading manufacture in this area, are used in the book.
Software The synthesis software used in the book is the Web version of the Xilinx ISE package. The functionality is of this version is similar to that of the full version but supports only a limited number of devices. Most introductory development boards use FPGA devices from the inexpensive Spartan-3 family. Since the Web version supports the Spartan-3 device, it fits our need. The simulation software used in the book is the starter version of Mentor Graphics’ ModelSim XE III package. It is a customized edition of ModelSim. Both software packages are free and can be downloaded from Xilinx’s Web site.
FPGA prototyping board This book is prepared to be used with several entry-level FPGA prototyping boards manufactured by Digilent Inc., including the Spartan-3 Starter, Nexys-2, and Basys boards, all of which contain a Spartan-3/3E FPGA device and have similar I/O peripherals. The design examples in the book are based on the Spartan-3 Starter board (or simply the S3 board), but most of them can be used directly in other boards as well. The applicability of the HDL codes is summarized below.
PC Accessories The design examples include interfaces to several PC peripheral devices. A keyboard, a mouse, and a VGA monitor are required for the respective modules, and a “straight-through” serial cable (the most commonly used type) is required for the DART module. These accessories are widely available and can probably be obtained from an old PC.
Book organization
The book is divided into three major parts. Part I introduces the elementary HDL constructs and their hardware counterparts, and demonstrates the construction of a basic digital circuit with these constructs. It consists of six chapters:
Part II applies the techniques from Part I to design an array of peripheral modules for the prototyping board. Each chapter covers the development, implementation, and verification of an individual peripheral. These modules can be incorporated to a larger project. Part II consists of seven chapters:
Part III introduces an FPGA-based soft-core microcontroller, known as Picolilaze, and demonstrates the integration of a general-purpose processor and customized circuit. It includes four chapters:
In addition to regular chapters, the appendix summarizes and lists all code templates.
Special marks Xilinx specific While the examples of this book are implemented on a Xilinx-based prototyping board and the codes are synthesized by Xilinx ISE software, we try to make the HDL codes device-independent and software-neutral as much as possible. Most discussions and codes can be applied to different target devices and different synthesis software as well. However, certain codes or device features are unique to Xilinx ISE software or Spartan-3 FPGA devices. We use the Xilinx specific superscript, as in the heading of this section, to indicate that the discussion in the corresponding section or chapter is unique to Xilinx.
Similarly, we use marginal notes, such as the one shown on the outer edge, to indicate that the discussion in the paragraph is unique to Xilinx. This note indicates that the code or design is no longer portable and needs to be revised when a different software package or target device is used.
Instructional use
The book can be a good companion text for an introductory digital systems course or an advanced project-oriented course. In an introductory digital systems course, the book supplies the lab portion of the curriculum. The chapters in Part I basically follow the sequence of a typical curriculum and can be presented along with regular lectures. One or two peripheral modules can be selected as case studies, and corresponding experiments can be used as term projects.
In an advanced project-oriented course, the book provides a base for independent projects. The materials in Part I should be treated as an overview or refresher, which provides a general background on HDL, synthesis, and FPGA boards. Some modules in Part II can be used to demonstrate the design of more complex circuits. These modules can also be considered as building blocks (i.e., IPs) or subsystems to be integrated into final projects. The PicoBlaze microcontroller in Part III can be used as general-purpose processor if an embedded-system type of project is desired.
Companion Web site
An accompanying Web site (http://academic.csuohio.edu/chu_p/rtl) provides additional information, including the following materials:
Errata The book is self-prepared, which means that the author has produced all aspects of the text, including illustrations, tables, code listings, indexing, and formatting. As errors are always bound to happen, the accompanying Web site provides an updated errata sheet and a place to report errors.
P. P. CHU
Cleveland, Ohio
October 2007
ACKNOWLEDGMENTS
The author would like to express his gratitude to Professor George L. Kramerich for his encouragement and help.
The author also thanks John Wiley & Sons, Inc. for giving permission to use Figures 3.1, 3.2, 4.2, 4.10, 4.11, and 6.5 from my text RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, and Xilinx, Inc. for giving permission to use Figures 2.3 and 8.3 from the Spartan-3 Starter Kit Board User Guide.
All trademarks used or referred to in this book are the property of their respective owners.
P. P. Chu
PART I BASIC DIGITAL CIRCUITS
CHAPTER 1
GATE-LEVEL COMBINATIONAL CIRCUIT
1.1 INTRODUCTION
VHDL stands for VHSIC (very high-speed integrated circuit) hardware description language. It was originally sponsored by the U.S. Department of Defense and later transferred to the IEEE (Institute of Electrical and Electronics Engineers). The language is formally defined by IEEE Standard 1076. The standard was ratified in 1987 (referred to as VHDL 87), and revised several times. This book mainly follows the revision in 1993 (referred to as VHDL93).
VHDL is intended for describing and modeling a digital system at various levels and is an extremely complex language. The focus of this book is on hardware design rather than the language. Instead of covering every aspect ofVHDL, we introduce the key VHDL synthesis constructs by examining a collection of examples. Detailed VHDL coverage may be explored through the sources listed in the Bibliography.
In this chapter, we use a simple comparator to illustrate the skeleton of a VHDL program. The description uses only logical operators and represents a gate-level combinational circuit, which is composed of simple logic gates. In Chapter 3, we cover the more sophisticated VHDL operators and constructs and examine module-level combinational circuits, which are composed of intermediate-sized components, such as adders, comparators, and multiplexers.
Table 1.1 Truth table of a I-bit equality comparator
| input i0 il |
output eq |
| 00 | 1 |
| 01 | 0 |
| 10 | 0 |
| 11 | 1 |
1.2 GENERAL DESCRIPTION
Consider a l-bit equality comparator with two inputs, i0 and i1, and an output, eq. The eq signal is asserted when i 0 and i 1 are equal. The truth table of this circuit is shown in Table 1.1.
Assume that we want to use basic logic gates, which include not, and, or, and xor cells, to implement the circuit. One way to describe the circuit is to use a sum-of-products format. The logic expression is
One possible corresponding VHDL code is shown in Listing 1.1. We examine the language constructs and statements of this code in the following subsections.
Listing 1.1 Gate-level implementation of a l-bit comparator
library ieee;
use ieee.std_logic_1164. all;
entity eq1 is
port (
5 i0, i1: in std_logic;
eq: out std_logic
) ;
end eq1;
10 architecture sop_arch of eq1 is
signal p0, p1: std_logic;
begin
— sum of two product terms
eq <= p0 or p1;
15 — product terms
P0 <= (not i0) and (not i1);
p1 <= i0 and i1;
end sop_arch;
1.2.1 Basic lexical rules
VHDL is case insensitive, which means that upper-and lowercase letters can be used interchangeably, and free formatting, which means that spaces and blank lines can be inserted freely. It is good practice to add proper spaces to make the code clear and to associate special meaning with cases. In this book, we reserve uppercase letters for constants.
An identifier is the name of an object and is composed of 26 letters, digits, and the underscore (_), as in i0, i1, and data_bus1_enable. The identifier must start with a letter.
The comments start with -- and the text after it is ignored. In this book, the VHDL keywords are shown in boldface type, as in entity, and the comments are shown in italics type, as in
--this is a commentt
1.2.2 Library and package
The first two lines,
library ieee;
use ieee.std_logic_1164. all;
invoke the std_logic_1164 package from the ieee library. The package and library allow us to add additional types, operators, functions, etc. to VHDL. The two statements are needed because a special data type is used in the code.
1.2.3 Entity declaration
The entity declaration
entity eq1 is
port (
i0, i1: in std_logic;
eq: out std_logic
) ;
end eq1;
essentially outlines the I/O signals of the circuit. The first line indicates that the name of the circuit is eq1, and the port section specifies the I/O signals. The basic format for an I/O port declaration is
signal_name1, signal_name2, ... : mode data_type;
The mode term can be in or out, which indicates that the corresponding signals flow into or out of of the circuit. It can also be inout, for bidirectional signals.
The mode term can be in or out, which indicates that the corresponding signals flow into or out of of the circuit. It can also be inout, for bidirectional signals.
1.2.4 Data type and operators
VHDL is a strongly typed language, which means that an object must have a data type and only the defined values and operations can be applied to the object. Although VHDL is rich in data types, our discussion is limited to a small set of predefined types that are suitable for synthesis, mainly the std_logic type and its variants.
std_logic type The std_logic type is defined in the std_logic_1164 package and consists of nine values. Three of the values, '0', '1', and 'Z', which stand for logical 0, logical 1, and high impedance, can be synthesized. Two values, 'U' and 'X', which stand for uninitialized and unknown (e.g., when signals with '0' and '1' values are tied together), may be encountered in simulation. The other four values, '-', 'H', 'L', and ,W' , are not used in this book.
A signal in a digital circuit frequently contains multiple bits. The s td.Logi c.vect.or data type, which is defined as an array with elements of std_Logic, can be used for this purpose. For example, let a be an 8-bit input port. It can be declared as
a: in std_logic_vector (7 downto 0);
We can use term like a(7 downto 4) to specify a desired range and term like a(1) to access a single element of the array. The array can also be declared in ascending order:
a: in std_logic_vector (0 to 7);
We generally avoid this format since it is more natural to associate the MSB with the leftmost position.
Logical operators Several logical operators, including not, and, or, and xor, are defined over the std_logic_vector and std_logic data type. Bit-wise operation is used when an operator is applied to an object with the std_logic_vector data type. Note that the and, or, and xor operators have the same precedence and we need to use parentheses to specify the desired order of evaluation, as in
(a and b) or (c and d)
1.2.5 Architecture body
The architecture body,
architecture sop_arch of eqi is
signal pO, pi: std_logic;
begin
— sum of two product terms
eq <= pO or pi;
— product terms
pO <= (not iO) and (not ii);
pi <= iO and ii;
end sop_arch;
describes operation of the circuit. VHDL allows multiple bodies associated with an entity, and thus the body is identified by the name sop_arch (sum-of-products architecture).
The architecture body may include an optional declaration section, which specifies constants, internal signals, and so on. Two internal signals are declared in this program:
signal pO, pi: std_logic;
The main description, encompassed between begin and end, contains three concurrent statements. Unlike a program in C language, in which the statements are executed sequentially, concurrent statements are like circuit parts that operate in parallel. The signal on the left-hand side of a statement can be considered as the output of that part, and the expression specifies the circuit function and corresponding input signals. For example, consider the statement
eq <= pO or p1;
It is a circuit that performs the or operation. When p0 or p1 changes its value, this statement is activated and the expression is evaluated. The new value is assigned to eq after the default propagation delay.
Figure 1.1 Graphical representation of a comparator program.
The graphical representation of this program is shown in Figure 1.1. The three circuit parts represent the three concurrent statements. The connections among these parts are implicitly specified by the signal and port names. The order of the concurrent statements is clearly irrelevant and the statements can be rearranged arbitrarily.
1.2.6 Code of a 2-bit comparator
We can expand the comparator to 2-bit inputs. Let the input be a and b and the output be aeqb. The aeqb signal is asserted when both bits of a and b are equal. The code is shown in Listing 1.2.
Listing 1.2 Gate-level implementation of a 2-bit comparator
library ieee;
use ieee. std_logic_1164. all;
entity eq2 is
port(
5 a, b: in std_logic_vector (1 downto 0);
aeqb: out std_logic
) ;
end eq2;
10 architecture sop_arch of eq2 is
signal p0,pl,p2,p3: std_logic;
begin
— sum of product terms
aeqb <= p0 or pl or p2 or p3;
15 — product terms
p0 <= ((not a (t)) and (not b(l))) and
( (not a (0)) and (not b (0) ) ) ;
P1 <= (( not a ( 1 )) and (n 0 t b ( 1) )) and (a (0) and b (0) ) ;
p2 <= (a (t) and b (l)) and ((not a (0) ) and (not b(0)));
20 p 3 <= (a ( 1 ) and b ( 1 )) and (a ( 0 ) and b ( 0 ) ) ;
end sop_arch;
The a and b ports are now declared as a two-element std_logic_vector. Derivation of the architecture body is similar to that of a I-bit comparator. The p0, p1, p2, and p3 signals represent the results of the four product terms, and the final result, aeqb, is the logic expression in sum-of-products format.
Figure 1.2 Construction of a 2-bit comparator from I-bit comparators.
1.3 STRUCTURAL DESCRIPTION
A digital system is frequently composed of several smaller subsystems. This allows us to build a large system from simpler or predesigned components. VHDL provides a mechanism, known as component instantiation, to perform this task. This type of code is called structural description.
An alternative to the design of the 2-bit comparator of Section 1.2.6 is to utilize the previously constructed l-bit comparators as the building blocks. The diagram is shown in Figure 1.2, in which two I-bit comparators are used to check the two individual bits and their results are fed to an and cell. The aeqb signal is asserted only when the two bits are equal.
The corresponding code is shown in Listing 1.3. Note that the entity declaration is the same and thus is not included.
Listing 1.3 Structural description of a 2-bit comparator
architecture struc_arch of eq2 is
signal e0, e1: std_logic;
begin
— ins tan t i ate two 1 - bit compara tor s
5 eq_bit0_unit: entity work. eq1 (sop_arch)
port map ( i 0 = >a (0), i 1 = >b ( 0), e q = >e0) ;
eq_bit1_unit: entity work. eq1 (sop_arch)
port map ( i 0 = >a ( 1), i 1 = >b ( 1), e q = > e 1 ) ;
— a and bare e qua I if individua I bits are equa I
10 aeqb <= e0 and e1;
end struc_arch;
The code includes two component instantiation statements, whose syntax is:
unit _label: en tity lib_name . entity _name (arch_name)
port map(
formal_signal=>actual_signal,
formal_signal=>actual_signal,
) ;
The first portion of the statement specifies which component is used. The unit_label term gives a unique id for an instance, the lib_name term indicates where (i.e., which library) the component resides, and the entity_name and arch_name terms indicate the names of the entity and architecture. The arch.name term is optional. If it is omitted, the last compiled architecture body will be used. The second portion is port mapping, which indicates the connection between formal signals, which are I/O ports declared in a component's entity declaration, and actual signals, which are the signals used in the architecture body.
The first component instantiation statement is
eq_bit0_unit: entity work.eq1(sop_arch)
port map ( i 0 =>a ( 0), i 1 =>b ( 0), eq =>e0) ;
The work library is the default library in which the compiled entity and architecture units are stored, and eq1 and sop.arch are the names of the entity and architecture defined in Listing 1.1. The port mapping reflects the connections shown in Figure 1.2. The component instantiation statement is also a concurrent statement and represents a circuit that is encompassed in a black box whose function is defined in another module.
This example demonstrates the close relationship between a block diagram and code. The code is essentially a textual description of a schematic. Although it is a clumsy way for humans to comprehend a diagram, it puts all representations into a single HDL framework. The Xilinx ISE package includes a simple schematic editor utility that can perform schematic capture in graphic format and then convert the diagram into an HDL structural description.
The component instantiation statement is added in VHDL 93. Older codes may use the mechanism in VHDL 87, in which a component must first be declared (i.e., made known) and then used. The code in this format is shown in Listing 1.4.
Listing 1.4 Structural description with VHDL-87
architecture vhd_87_arch of eq2 is
— compo n e n t dec I a rat ion
component eq1
port (
5 i0, i1: in std_logic;
eq: out std_logic
) ;
end component;
signal eO, el: std_logic;
10 begin
-- instantiate two 1 - bit comparators
eq_bit0_unit: eql -- use the declared name, eql
port map ( i 0 =>a ( 0), i 1 =>b ( 0), eq => e0) ;
eq_bitl_unit: eql -- use the declared name, eql
15 por t map ( i 0 =>a ( 1), i 1 =>b ( 1), e q =>e 1 ) ;
-- a and bare e qua I if individua I bits are equa I
aeqb <= eO and el;
end vhd_87_arch;
Note that the original clause,
eq_bit0_unit: entity work. eql (sop_arch)
is replaced by a clause with the declared component name
eq_bit0_unit: eq1
Figure 1.3 Testbench for a 2-bit comparator.
1.4 TESTBENCH
After code is developed, it can be simulated in a host computer to verify the correctness of the circuit operation and can be synthesized to a physical device. Simulation is usually performed within the same HDL framework. We create a special program, known as a testbench, to mimic a physical lab bench. The sketch of a 2-bit comparator testbench program is shown in Figure 1.3. The uut block is the unit under test, the test vector generator block generates testing input patterns, and the monitor block examines the output responses.
A simple testbench for the 2-bit comparator is shown in Listing 1.5.
Listing 1.5 Testbench for a 2-bit comparator
The code consists of a component instantiation statement, which creates an instance of a 2-bit comparator, and a process statement, which generates a sequence of test patterns.
The process statement is a special VHDL construct in which the operations are performed sequentially. Each test pattern is generated by three statements. For example,
-- test vector 2
test_ina <= “01”;
test_in1 <= “00”;
wait for 200 ns;
The first two statements specify the values for the test_in0 and test_in1 signals, and the third indicates that the two values will last for 200 ns.
The code has no monitor. We can observe the input and output waveforms on a simulator's display, which can be treated as a virtual logic analyzer. The simulated timing diagram of this testbench is shown in Figure 2.16.
Writing code for a comprehensive test vector generator and a monitor requires detailed knowledge of VHDL and is beyond the scope of this book. This listing can serve as a testbench template for other combinational circuits. We can substitute the uut instance and modify the test patterns according to the new circuit.
1.5 BIBLIOGRAPHIC NOTES
A short bibliographic section appears at the end of each chapter to provide some of the most relevant references for further exploration. A comprehensive bibliography is included at the end of the book.
VHDL is a complex language. The Designer's Guide to VHDL by P. J. Ashenden provides detailed coverage of the language's syntax and constructs. The author's RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability provides a comprehensive discussion on developing effective, synthesizable codes. The derivation of the testbench for a large digital system is a difficult task. Writing Testbenches: Functional Verification of HDL Models, 2nd edition, by J. Bergeron focuses on this topic.
1.6 SUGGESTED EXPERIMENTS
At the end of each chapter, some experiments are suggested as exercises. The experiments help us to better understand the concepts and provide a hands-on opportunity to design and debug actual circuits.
1.6.1 Code for gate-level greater-than circuit
Develop the HDL codes in Experiment 2.9.1. The code can be simulated and synthesized after we complete Chapter 2.
1.6.2 Code for gate-level binary decoder
Develop the HDL codes in Experiment 2.9.2. The code can be simulated and synthesized after we complete Chapter 2.