reading

Cover
Title Page
Preface
1 Introduction
1. 1.1 Personalized Biomedical Diagnosis
2. 1.2 CMOS Sensor‐based Lab‐on‐a‐Chip for System Miniaturization
3. 1.3 Objectives and Organization of this Book
4. References
2 CMOS Sensor Design
1. 2.1 Top Architecture
2. 2.2 Noise Overview
3. 2.3 Pixel Readout Circuit
4. 2.4 Column Amplifier
5. 2.5 Column ADC
6. 2.6 Correlated Sampling
7. 2.7 Timing Control
8. 2.8 LVDS Interface
9. References
3 CMOS Impedance Sensor
1. 3.1 Introduction
2. 3.2 CMOS Impedance Pixel
3. 3.3 Readout Circuit
4. 3.4 A 96 × 96 Electronic Impedance Sensing System
5. References
4 CMOS Terahertz Sensor
1. 4.1 Introduction
2. 4.2 CMOS THz Pixel
3. 4.3 Readout Circuit
4. 4.4 A 135 GHz Imager
5. 4.5 Plasmonic Sensor for Circulating Tumor Cell Detection
6. References
5 CMOS Ultrasound Sensor
1. 5.1 Introduction
2. 5.2 CMUT Pixel
3. 5.3 Readout Circuit
4. 5.4 A 320 × 320 CMUT‐based Ultrasound Imaging System
5. References
6 CMOS 3‐D‐Integrated MEMS Sensor
1. 6.1 Introduction
2. 6.2 MEMS Sensor
3. 6.3 Readout Circuit
4. 6.4 A 3‐D TSV‐less Accelerometer
5. References
7 CMOS Image Sensor
1. 7.1 Introduction
2. 7.2 CMOS Image Pixel
3. 7.3 Readout Circuit
4. 7.4 A 3.2 Mega CMOS Image Sensor
5. References
8 CMOS Dual‐mode pH‐Image Sensor
1. 8.1 Introduction
2. 8.2 CMOS Dual‐mode pH‐Image Pixel
3. 8.3 Readout Circuit
4. 8.4 A 64 × 64 Dual‐mode pH‐Image Sensor
5. References
9 CMOS Dual‐mode Energy‐harvesting‐image Sensor
1. 9.1 Introduction
2. 9.2 CMOS EHI Pixel
3. 9.3 Readout Circuit
4. 9.4 A 96 × 96 EHI Sensing System
5. References
10 DNA Sequencing
1. 10.1 Introduction
2. 10.2 CMOS ISFET‐based Sequencing
3. 10.3 CMOS THz‐based Genotyping
4. 10.4 Beyond CMOS Nanopore Sequencing
5. 10.5 Summary
6. References
11 Cell Counting
1. 11.1 Introduction
2. 11.2 Optofluidic Imaging System
3. 11.3 Super‐resolution Image Processing
4. 11.4 Machine‐learning‐based Single‐frame Super‐resolution
5. 11.5 Microfluidic Cytometer for Cell Counting
6. References
12 Conclusion
1. 12.1 Summaries
2. 12.2 Future Works
Index
End User License Agreement

List of Tables

Chapter 03
1. Table 3.1 Extracted parameter from equivalent circuit model.
Chapter 05
1. Table 5.1 Design Parameters for CMUT.
2. Table 5.2 Measured transceiver front‐end IC performance.
Chapter 06
1. Table 6.1 Specifications summary of the vertically bonded MEMS/CMOS chip.
Chapter 07
1. Table 7.1 Performances summary of BSI‐CIS.
Chapter 08
1. Table 8.1 Dual‐mode sensor chip design specifications.
2. Table 8.2 Comparison of state‐of‐the‐art ISFET sensors.
Chapter 09
1. Table 9.1 Performance summary of the EHI imager
2. Table 9.2 Performance summary of the EHI imager circuit blocks in IM on 1 V supply
3. Table 9.3 Performance summary in EHM
4. Table 9.4 Comparison of proposed imager to other EHIs
Chapter 10
1. Table 10.1 Summary of protein and solid‐state nanopore parameters.
2. Table 10.2 Summary of DNA detection methods.
Chapter 11
1. Table 11.1 Pseudo code for ELMSR.
2. Table 11.2 Pseudo code for CNNSR.
3. Table 11.3 Measured counting results of mixed RBC and HepG2 sample.

List of Illustrations

Chapter 01
1. Figure 1.1 Global aging trends for the percentage of the total population at 60 years of age or over in 2012 and 2050 [1].
2. Figure 1.2 A typical microscope and its optical path with objective lens and eye piece. To reach high‐resolution imaging capability, bulky, expensive, and sophisticated lenses are required.
3. Figure 1.3 Diagrams of: (a) Optical‐based; and (b) Electrochemical‐based flow cytometry.
4. Figure 1.4 BD FACSCount™ cell cytometer system.
5. Figure 1.5 A typical optical DNA sequencer.
6. Figure 1.6 CMOS‐based LOC integration for biomedical instrument miniaturization.
7. Figure 1.7 Cross‐section view (left) and symbol (right) of CMOS technology components: NMOS and PMOS.
8. Figure 1.8 Process flow for the fabrication of an n‐type MOSFET on p‐type silicon.
9. Figure 1.9 Diagrams of biochemical sensing structures; the sensing parts are: (a) p‐n junction; (b) Passivation; and (c) Metal electrode pair.
10. Figure 1.10 A typical architecture diagram of a CMOS sensor.
11. Figure 1.11 The concept of the optical and potential dual‐mode CMOS image sensor.
12. Figure 1.12 Schematic of the multimodal optical and pH CMOS image sensor.
13. Figure 1.13 A typical microfluidic channel.
14. Figure 1.14 Cross‐sectional schematic of a unit cell on digital microfluidic arrays.
15. Figure 1.15 Microfluidic channel masks designed by AutoCAD.
16. Figure 1.16 PDMS mold fabrication process.
17. Figure 1.17 Microfluidic channel fabrication process using the soft lithography technique.
Chapter 02
1. Figure 2.1 A typical CMOS sensor architecture.
2. Figure 2.2 Resistor thermal noise model.
3. Figure 2.3 MOSFET thermal noise model in strong inversion region.
4. Figure 2.4 MOSFET conductive channel cross‐section view in (a) triode and (b) saturation region.
5. Figure 2.5 MOSFET flicker noise model.
6. Figure 2.6 Diode shot noise model.
7. Figure 2.7 MOSFET noise model with: (a) separate; and (b) equivalent noise.
8. Figure 2.8 (a) Source follower with active load; and (b) The corresponding small signal circuit.
9. Figure 2.9 (a) Pixel readout structure of a 2 T source‐follower pixel; and (b) The corresponding transfer curve.
10. Figure 2.10 Pixel readout structures of (a) a 4 T SF pixel; and (b) a 1.75 T 4‐shared source‐follower pixel. (c) Timing diagram and transfer curve of (b).
11. Figure 2.11 Schematic of a sub‐threshold Gm integrator pixel readout structure.
12. Figure 2.12 The corresponding timing diagram and transfer curve.
13. Figure 2.13 Schematic of a 4‐shared sub‐threshold Gm integrator pixel readout structure.
14. Figure 2.14 (a) Schematic of capacitive transimpedance amplifier (CTIA); The corresponding; (b) Timing diagram; and (c) Current‐to‐voltage transfer curve.
15. Figure 2.15 Schematic of: (a) A simple 5‐T operational transconductance amplifier (OPA); and (b) Folded‐cascode OTA.
16. Figure 2.16 Schematic of an in‐pixel CTIA readout structure.
17. Figure 2.17 (a) Schematic of a multi‐gain switched capacitor amplifier. (b) The corresponding timing diagram and voltage transfer curve.
18. Figure 2.18 (a) Schematic of a single‐slope ADC; and (b) The corresponding timing diagram.
19. Figure 2.19 (a) Diagram of the 3‐stage comparator, including two (b) differential pre‐amplifiers; and one (c) Schmitt Trigger comparator.
20. Figure 2.20 Schematic of a ramp generator.
21. Figure 2.21 (a) Schematic of a simple hysteresis comparator; and (b) The corresponding hysteresis voltage transfer curves.
22. Figure 2.22 (a) Schematic of a 3‐bit bidirectional counter; and (b) The corresponding timing diagram.
23. Figure 2.23 (a) Quantization transfer curve with a continuous ramp as input signal and the corresponding quantization error during conversion; and (b) Block diagram of a linear model of quantizer.
24. Figure 2.24 Quantization noise power spectrum density distribution of Nyquist‐rate sampling and oversampling.
25. Figure 2.25 (a) A first‐order sigma‐delta modulator; and (b) The corresponding frequency domain model.
26. Figure 2.26 Noise shaping property of sigma‐delta modulator.
27. Figure 2.27 Schematic of continuous‐time: (a) Gm‐C filter; and (b) Active‐RC filter.
28. Figure 2.28 (a) Schematic of a discrete‐time switched‐capacitor filter; and (b) Its operations in different clock phases.
29. Figure 2.29 Implementation of: (a) A triode‐based transconductor; and (b) A 2‐stage operational amplifier.
30. Figure 2.30 Implementation of a first‐order sigma‐delta ADC.
31. Figure 2.31 A schematic example that CDS and CMS are performed.
32. Figure 2.32 Timing diagram of correlated double sampling (CDS).
33. Figure 2.33 Timing diagram of correlated multiple sampling (CMS).
34. Figure 2.34 Two ways to realize a 5‐input NAND logic block.
35. Figure 2.35 Diagram of a 3‐8 decoder.
36. Figure 2.36 Diagram of a hierarchy 7‐128 decoder.
37. Figure 2.37 Block diagram and timing diagram of a row driver.
38. Figure 2.38 Schematic of a typical level shifter.
39. Figure 2.39 Schematic of data readout blocks following ADC.
40. Figure 2.40 Schematic of a SRAM cell.
41. Figure 2.41 Schematic of Sense Amplifier (SA).
42. Figure 2.42 Diagram of a typical LVDS.
43. Figure 2.43 Differential input signals generation circuit.
44. Figure 2.44 (a) Diagram of a LVDS driver circuit; and (b) Simple common‐mode feedback circuit.
Chapter 03
1. Figure 3.1 (a) CMOS impedance sensor pixel array; (b) Cross‐sectional illustration of the sensing and addressing scheme of the CMOS impedance pixel; and (c) 96 × 96 impedance sensing electrode array.
2. Figure 3.2 (a) Sectional view of an electrode covered with an MCF‐7 cell. The total current is split into three pathways: I_spread, I_cell, and I_seal. The equivalent circuit of (b) Electrode without cells; and (c) Electrode with cells.
3. Figure 3.3 Block diagram of the CMOS impedance sensor readout circuit.
4. Figure 3.4 Block diagram of a transimpedance amplifier as readout circuit for the shared pixel array.
5. Figure 3.5 Circuit schematic of pixel‐level transimpedance amplifier.
6. Figure 3.6 Circuit schematic of the column‐level column‐readout amplifier.
7. Figure 3.7 Architecture of the 96 × 96 Electronic Impedance Sensing System.
8. Figure 3.8 Electrical‐impedance spectroscopy (EIS) platform for the detection and enumeration of CTCs: (a) Optical image of high‐density CMOS electrodes surrounded with silicone glob top to make a chamber. The ITO coated glass is positioned on top of the chamber to act as a counter electrode; (b) Zoomed optical image of post‐processed CMOS microelectrode array with exposed gold capping for bio‐sensing; and (c) Cross‐sectional scanning electron micrograph of a 22‐m wide microelectrode with 6 stacks of metal layers. A 0.1‐m thick Ti adhesion layer is sandwich between Au and Al (not shown).
9. Figure 3.9 (a) Impedance spectroscopy of electrode with cell attached in cell buffer; (b) Impedance spectroscopy of electrode without cell attached in cell buffer. The black circles represent impedance spectrum of electrode without cell in pure PBS; (c) Percentage of normalized impedance change as a function of measured frequency; (d) Statistical normalized impedance changes with the presence and absence of cell on microelectrode (n = 45 over three chip with cell, n = 47 over three chip without cell). The inset shows an optical image of microelectrodes with presence of cells (left column) and absence of cell (right column).
10. Figure 3.10 Calculated impedance magnitude as a function of frequency for 22 µm² electrode covered with cells: (a) Impedance evolution when R_seal increases for cell covered electrode, and (b) Normalized impedance change as a function of frequency. Each line corresponds to values of R_seal in the range of 0.14–0.84 MΩ.
11. Figure 3.11 (a) Optical image of cells seeded on a 12 × 12 microelectrode array; (b) Optical mapping; and (c) Impedance mapping of cells on the microelectrode array. The dark and gray square denote the status of an individual electrode; (d) The categories plot shows the accuracy of impedance mapping from an array of 144 pixels. A mapping accuracy of 90% was achieved.
Chapter 04
1. Figure 4.1 Application examples of THz spectroscopy and imaging: (a) Nondestructive detection of crack initiation in a film‐coated layer on a swelling tablet [5]; (b) Hydration state characterization in solution [6]; (c) In‐vitro breast cancer diagnosis [7]; and (d) In‐vivo skin cancer diagnosis [8].
2. Figure 4.2 (a) Stacked SRR unit‐cell designed by metal layers of M7 and M6; and (b) S21 simulation results with different stacking methods.
3. Figure 4.3 Geometries of resonators with slow‐wave shielding: (a) Differential T‐line loaded with stacked SRR; (b) T‐line based standing‐wave resonator; and (c) Cross‐section of BEOL.
4. Figure 4.4 T‐line‐based SRR excitation: (a) Single‐ended approach; (b) Differential approach; (c) Magnetic field distribution of single‐ended approach; and (d) Magnetic field distribution of differential approach.
5. Figure 4.5 Reflection coefficients of both single ended and differential resonators.
6. Figure 4.6 Simulated Γ and quality factor (Q) of SRR/T‐line unit cell at resonance.
7. Figure 4.7 On‐chip differential T‐line loaded with CSRR.
8. Figure 4.8 EM characterization of the proposed differential CSRR resonator.
9. Figure 4.9 Simplified equivalent circuit model of super‐regenerative amplifier.
10. Figure 4.10 Reflection coefficient of T‐line loaded with CSRR unit‐cells.
11. Figure 4.11 Reflection loss compensation by cross‐coupled NMOS pair with controlled tail current.
12. Figure 4.12 Layout for CMOS on‐chip implementation of DTL‐CSRR for 96 GHz SRX.
13. Figure 4.13 EM‐simulation based comparison of DTL‐CSRR and LC‐tank resonator for CMOS 96 GHz SRX design.
14. Figure 4.14 Schematic of CMOS 96 GHz SRX with DTL‐CSRR.
15. Figure 4.15 Layout for CMOS on‐chip implementation of DTL‐SRR for 135 GHz SRX.
16. Figure 4.16 EM‐simulation‐based comparison of DTL‐SRR and LC‐tank resonator for CMOS 135 GHz SRX design.
17. Figure 4.17 Impedance diagram of DTL‐SRR and LC‐Tank in Globalfoundries 65‐nm CMOS process: (a) Real and imaginary parts of Z_Diff; (b) Phase of Z_Diff; and (c) Phase of Z_Diff when the ideal 16‐fF capacitor is included.
18. Figure 4.18 Schematic of CMOS 135 GHz SRX with DTL‐SRR.
19. Figure 4.19 (a) PCB integration of CMOS 135‐GHz SRX with antenna; and (b) THz imaging measurement setup with the proposed receiver chip integrated on PCB and object under test fixed on an X‐Y moving stage.
20. Figure 4.20 Images captured by imaging system with the proposed 135‐GHz SRX receiver: animal skin samples and Panadol pills.
21. Figure 4.21 Images captured by imaging system with the proposed 135‐GHz SRX receiver: various types of oil.
22. Figure 4.22 Absorption ratio of various types of oil detected at 135 GHz.
23. Figure 4.23 CMOS sub‐THz cell impedance detection system.
24. Figure 4.24 The simplified equivalent circuit and the route to extract the cell dielectric parameters using a SRR biosensor loaded with CTCs solutions.
25. Figure 4.25 The schematic diagram of SRR‐based‐oscillator sensor.
26. Figure 4.26 THz chip in the 65 nm process for CTC detection.
27. Figure 4.27 The outputs of oscillator and charge accumulator based on circuit simulation.
28. Figure 4.28 The voltage outputs under various capacitance values of loaded CTC solution. The inset shows the relationship between voltage output and loaded capacitance.
Chapter 05
1. Figure 5.1 Overall system diagram of an ultrasound imaging system with an AFE receiver integrating with the capacitive micro‐machined ultrasound transducer (CMUT).
2. Figure 5.2 (a) Diagram of 2‐D CMUT array; (b) One CMUT element; (c) One CMUT cell; (d) Cross‐section view of CMUT cell; and (e) Top view of CMUT cells.
3. Figure 5.3 Equivalent simulation model for CMUT.
4. Figure 5.4 Two‐channel analog front‐end IC unit cell consisting of two HV pulsers, two HV protection switches, and a shared low‐noise preamplifier.
5. Figure 5.5 Overall system floor plan for 2‐D multi‐channel analog front‐end IC.
6. Figure 5.6 Timing diagram of analog front‐end operation.
7. Figure 5.7 Block diagram of transmitter front‐end IC.
8. Figure 5.8 Schematic of 1.8‐to‐5 V level‐shifter.
9. Figure 5.9 Schematic of 5‐to‐25 V level‐shifter and HV output driver.
10. Figure 5.10 Schematic of the low‐noise preamplifier.
11. Figure 5.11 Simulated timing response of the HV transmitter front‐end.
12. Figure 5.12 Simulated: (a) closed‐loop frequency response; and (b) Input referred noise current.
13. Figure 5.13 Chip microphotograph of: (a) AFE array; and (b) 2‐channel AFE IC cell.
14. Figure 5.14 Measured transient response of the HV pulser.
15. Figure 5.15 Measured: (a) Frequency response; and (b) Input noise current of the preamplifier.
16. Figure 5.16 Acoustic transmission testing setup for the implemented ultrasound sensor and fabricated CMUT sample.
17. Figure 5.17 Measured hydrophone output voltage signal.
18. Figure 5.18 Acoustic pulse‐echo testing setup for implemented AFE IC and fabricated CMUT sample.
19. Figure 5.19 Measured pulse‐echo response.
Chapter 06
1. Figure 6.1 The MEMS capacitive accelerator is fabricated on an SOI wafer using DRIE and release. The single layer of patterned metal consists of an electrical contact pad and a hermetic seal is used. Electrical feed‐through is routed through the on‐chip interconnect in the CMOS chip.
2. Figure 6.2 System block diagram for the readout circuit.
3. Figure 6.3 Schematic diagram of the low noise, band‐pass gain stage, which consists of two single‐ended output amplifiers based on folded‐cascode architecture. Pseudo‐resistors are used in the feedback path of the amplifiers. Tunable feedback capacitance allows variable gain.
4. Figure 6.4 Die micrograph of the readout circuit fabricated through MPW (0.35 µm, 2P4M process).
5. Figure 6.5 Heterogeneous 3‐D CMOS‐on‐MEMS stacking with face‐to‐face direct metal bonding (no solder) that realizes electrical, mechanical, and hermetic bonds simultaneously.
6. Figure 6.6 (a) FIB/SEM image showing the on‐chip metal layers in the CMOS chip; and (b) Since no solder bumping is applied, the top passivation layer is intentionally recessed to create a standoff gap for the metal pads to facilitate direct metal bonding (thermo‐compression) with the matching pads on the MEMS chip.
7. Figure 6.7 (a) Cross‐sectional view of the bonded Al–Au layer from dummy structure; (b) High resolution TEM view; (c) EDX elemental mapping of the bonded layer; and (d) EDX line scan results.
8. Figure 6.8 (a) The alignment marks on MEMS and CMOS die are used for orienting the dies before stacking; and (b) The CMOS die is vertically stacked on top of the MEMS die.
9. Figure 6.9 The face‐to‐face bonded CMOS chip on MEMS chip. The bonded chip is then wire bonded to the package for electrical testing.
10. Figure 6.10 Shear strength test results with varying bonding temperature.
11. Figure 6.11 Shear strength test results with varying bonding temperature C‐SAM image of samples bonded at 290 °C.
12. Figure 6.12 Schematics of the formation of a sealed cavity for helium leak rate detection: (a) Forming of cavities, seal rings, and air channel using DRIE; (b) Sequential deposition of Cr layer and Au bonding layer; (c) Deposition of SiO₂ isolation and Al bonding layer; and (d) Au–Al thermo‐compression bonding of the cavity wafer to the capping wafer.
13. Figure 6.13 C‐SAM images of hermetic test dies.
14. Figure 6.14 (a) The band‐pass gain stage output (upper trace) during the standalone testing of the CMOS readout, when one of the carrier amplitude is 7.5 Vpp (lower trace) at 50 kHz frequency and 0 g acceleration; and (b) Fully rectified sinusoids at the synchronous demodulator outputs, verifying that the readout is working as intended.
15. Figure 6.15 The gain stage output (yellow, upper trace) when the excitation carrier amplitude is 1 Vpp (blue, lower trace) at 50 kHz frequency and the bonded chip is tilted at: (a) 0 g; (b) +1 g; and (c) –1 g orientation. Acceleration at a tilt angle θ is given by g sin(θ).
16. Figure 6.16 Variation in the mean demodulator output with g at various carrier frequencies for the bonded chip.
17. Figure 6.17 FFT spectrum showing fundamental peak at the carrier frequency and higher‐order harmonics at integer multiples of carrier frequency.
18. Figure 6.18 (a) SNR as a function of carrier frequency at various g orientations, when the carrier amplitude is 1 Vpp; and (b) Output voltage noise as a function of carrier frequency at various g orientations, when the carrier amplitude is 1 Vpp.
19. Figure 6.19 Setup for the 500 g shock test. The chip is subjected to a maximum vertical acceleration of 503.55 g for a short duration of 1.03 m for a total number of 10 times.
20. Figure 6.20 General control profile during the 500 g and 1 ms mechanical shock test.
Chapter 07
1. Figure 7.1 CCD read out architecture.
2. Figure 7.2 CCD charge transfer operations.
3. Figure 7.3 Passive and active pixel schematic and potential well diagram.
4. Figure 7.4 (a) Architecture of a typical digital imaging system with CCD sensor; and (b) CIS chip integrates pixel, analog readout and digital control.
5. Figure 7.5 FSI 4 T pinned PD pixel structure: (a) Pixel Schematic; and (b) CIS chip cross‐section (Samsung NX200).
6. Figure 7.6 (a) Potential well diagram during pixel readout; and (b) Timing diagram during pixel readout.
7. Figure 7.7 Backside illuminated (BSI) 4 T CIS pixel structure: (a) Schematic; and (b) Cross‐section of CIS chip (OmniVision).
8. Figure 7.8 Stacked CIS: (a) Structure of stacked CIS; and (b) Cross‐sectional view of stacked CIS.
9. Figure 7.9 Photon transfer curve (PTC) showing different noise sources at the CIS imaging system.
10. Figure 7.10 Small signal model for the noise analysis in CIS.
11. Figure 7.11 CIS readout circuit structure.
12. Figure 7.12 CIS Global readout circuit.
13. Figure 7.13 CDS implementation by integrating switch‐capacitor amplifier with column sample and hold circuitry.
14. Figure 7.14 Contact imaging using: (a) FSI sensor, where PDs are far from the cell: and (b) BSI sensor, where the PDs are close to the cell.
15. Figure 7.15 Detail 4‐way shared no‐row‐select pixel structure of the BSI image sensor. Four PDs form a unit cell.
16. Figure 7.16 System architecture of the 3.2‐Mega‐Pixels CIS with top‐bottom readout scheme and 4.4‐ column pitch column readout circuit.
17. Figure 7.17 Block diagram of column readout flow and circuit.
18. Figure 7.18 Timing diagram of 3.2 Mega BSI‐CIS.
19. Figure 7.19 Photos of: (a) Setup of the developed microfluidic cytometer system; (b) Die micrograph of BSI CIS; and (c) Microfluidic channel mounted on the ceramic packaged sensor.
20. Figure 7.20 Measurement results of: (a) ADC output codes under different input voltages; and (b) BSI‐CIS sensor sensitivity.
21. Figure 7.21 ADC outputs of a 2.8 V reset voltage, a 2.2 V pixel signal and the subtraction of the two voltages.
22. Figure 7.22 Captured raw images of (a) WBC and (c) RBC and PLT. Processed images of (b) WBC and (d) RBC and PLT.
23. Figure 7.23 Captured contact images of WBC, RBC, and PLT, with microscope images as references.
Chapter 08
1. Figure 8.1 Contact imaging principle: with light source illuminated from above; the contact shadow images of microbeads can be captured by the sensor underneath.
2. Figure 8.2 Schematic of: (a) 4 T‐CIS pixel; (b) Dual‐mode pixel; and (c) ISFET pixel.
3. Figure 8.3 (a) Cross‐section layout of the dual‐mode CMOS ISFET pixel; and (b) The top view of the dual‐model pixel.
4. Figure 8.4 CDS readout schematic for dual‐mode sensor.
5. Figure 8.5 CDS readout timing diagram for both: (a) Optical mode; pH mode; and (b) before and (c) after loading solution.
6. Figure 8.6 Top architecture of dual‐mode sensor.
7. Figure 8.7 The global core amplifier circuit.
8. Figure 8.8 12‐bit pipelined ADC architecture.
9. Figure 8.9 Micrograph photo of the dual‐mode sensor chip and testing setup.
10. Figure 8.10 Cross‐sectional structure of the ISFET, as modeled in Sentaurus TCAD. The electron concentration during ISFET operation is indicated by coloring.
11. Figure 8.11 ISFET device simulation results showing the V_T change.
12. Figure 8.12 The global amplifier AC simulation results.
13. Figure 8.13 12‐bit pipelined ADC INL/DNL simulation results.
14. Figure 8.14 The correlated maps of distributed microbeads: (a) Contact images; and (b) pH values.
15. Figure 8.15 Measurement results: pH sensitivity of dual‐mode ISFET sensor.
16. Figure 8.16 The comparison with commercial pH meter for bacteria (E. Coli) culture solution with glucose at different time intervals.
17. Figure 8.17 Measurement results: spatial FFT of readout voltage variations: (a) with CDS; and (b) without CDS read out.
Chapter 09
1. Figure 9.1 Dual‐mode CMOS EHI APS pixel: (a) Circuit schematic; (b) Energy harvesting mode (EHM) configuration; and (c) Imaging mode (IM) configuration.
2. Figure 9.2 Proposed EHI CMOS APS pixel: (a) Layout; and (b) Cross‐section.
3. Figure 9.3 (a) Global and column level analog readout circuits; and (b) Current mirror OTA schematic used in GCA.
4. Figure 9.4 The schematics of the 10‐bit SAR ADC and two‐stage dynamic comparator.
5. Figure 9.5 (a) Ultra‐low power CIS architecture; and (b) Chip photo.
6. Figure 9.6 Global, row, and pixel level circuits for reset and select boosting in 3 T CMOS APS imagers.
7. Figure 9.7 Schematic of current‐mirror OTA.
8. Figure 9.8 Low‐power dynamic comparator in SAR ADC.
9. Figure 9.9 (a) Circuit diagram of the PMS; and (b) Operation principle of the PMS.
10. Figure 9.10 Simulation result of the full operating cycles of the PMS.
11. Figure 9.11 Power consumption of the EHI imager for varying frame rates (a) and varying supply voltages (b).
12. Figure 9.12 FoM performance of the imager under different frame rates and supply voltages.
13. Figure 9.13 Measured output voltage vs. output current (a) and output power of the solar cell array (b).
14. Figure 9.14 Measured efficiency of boost converter and overall PMS block.
15. Figure 9.15 Measured storage capacitor voltage (V_OUT) and V_START signals.
Chapter 10
1. Figure 10.1 The relationship between DNA sequence cost and Moore’s law: Data from the NHGRI Genome Sequencing Program (GSP): Available at: www.genome.gov/sequencingcosts.
2. Figure 10.2 A typical DNA molecule structure.
3. Figure 10.3 ISFET‐based sequencing principle.
4. Figure 10.4 DNA sample preparation process.
5. Figure 10.5 (a) PCR components; and (b) PCR process.
6. Figure 10.6 pH‐based DNA sequencing diagram (left); Cross‐section of ISFET during sequencing (right).
7. Figure 10.7 Output voltage in one microwell during the DNA sequencing procedure.
8. Figure 10.8 pH changes of different multi‐base incorporations.
9. Figure 10.9 Dual‐mode sensor to deal with pH crosstalk (left); Cross‐section of dual‐mode pixel with microbead contact imaging and ion sensing (right).
10. Figure 10.10 Diagram of THz‐based genotyping.
11. Figure 10.11 Realization diagram of metamaterial based THz‐sensing system.
12. Figure 10.12 Structure of (a) α‐HL protein; and (b) MspA protein;
13. Figure 10.13 Structure and cross‐section view of a Si₃N₄ nanopore.
14. Figure 10.14 A typical nanopore sequencing principle.
15. Figure 10.15 Equivalent nanopore model with a pair of electrodes.
16. Figure 10.16 A typical nanopore ion current sensing diagram.
17. Figure 10.17 Post process to deposit Ag/AgCl on read electrode array.
18. Figure 10.18 A typical procedure to assemble proteins and a sensor chip.
19. Figure 10.19 A typical Si₃N₄ nanopore array fabrication process.
20. Figure 10.20 Si₃N₄ nanopore array and IC readout chip integration.
Chapter 11
1. Figure 11.1 General lensless cell counting system setup based on CMOS image sensor (CIS): (a) Lensless cell imaging principle; (b) Cross‐sectional view of the lensless system; and (c) Concept of the machine‐learning based single‐frame super‐resolution (SR) processing.
2. Figure 11.2 Resolution model for lensless microfluidic imaging system.
3. Figure 11.3 Working principle of multi‐frame SR processing.
4. Figure 11.4 Working principle of the proposed single‐frame SR algorithm.
5. Figure 11.5 Structure of the ELM model.
6. Figure 11.6 ELM‐SR processing flowchart. The training is performed off‐line to generate a reference model that can map the interpolated LR images with the HF components from the HR images; and the testing is performed on‐line to recover an SR image from the input LR image with the reference model.
7. Figure 11.7 CNNSR processing flow including one off‐line training and one on‐line testing step.
8. Figure 11.8 Contact‐imaging based microfluidic cytometer for flowing cell recognition and counting, (a) Process of bonding with PDMS chip; and (b) Microfluidic cytometer system diagram.
9. Figure 11.9 Hardware design of the microfluidic cytometer: (a) PCB schematic; (b) PCB hardware with size of 5.6 cm × 5.6 cm; and (c) Control GUI of the microfluidic cytometer.
10. Figure 11.10 Flowing cell recognition flowchart. The detected LR image is processed with ELM‐SR to obtain SR images according to different off‐line trained models. Then, the SR images are compared with typical HR cell images in the library with cells categorized to one type that has the largest MSSIM.
11. Figure 11.11 Comparison of concentration measurement results for 6 µm microbead solution between the developed microfluidic cytometer and the commercial flow cytometer.
12. Figure 11.12 Comparison of counting results of different microbead concentration solutions between the developed microfluidic cytometer and the commercial flow cytometer: (a) Measurement results correlate well between the developed system and the commercial one (y = 0.97x – 8, correlation coefficient = 0.996); (b) The Bland‐Altman analysis of the measurement results between the developed one and the commercial one show a mean bias of –13.6 uL⁻¹, the lower 95% limit of agreement by –61.0 uL⁻¹, and the upper 95% limit of agreement by 33.8 uL⁻¹.
13. Figure 11.13 Example images of HepG2, RBC, and WBC in ELMSR and CNNSR training image libraries: (a) Original HR images with all HF details in ELMSR library; (b) Down‐sampled LR images with HF information lost in ELMSR library; (c) Interpolated LR images whose HF cannot be recovered in ELMSR library; (d) HF components that are lost during down‐sampling in the ELMSR library; (e) Original HR images with all HF details in the CNNSR library; (f) Down‐sampled LR images with HF information lost in the CNNSR library; (g) Interpolated LR images whose HF cannot be recovered in the ELMSR library; and (h) HF components that are lost during down‐sampling.
14. Figure 11.14 Example of HepG2, RBC, and WBC images in ELMSR and CNNSR testing: (a) Raw LR images captured by FSI CIS with pixel pitch 2.2 um; (b) Interpolated LR images; (c) ELMSR recovered HR images; (d) Raw LR images captured by BSI CIS with pixel pitch 1.1 µm; (e) Interpolated LR images; and (f) CNNSR recovered HR images, showing better performance in resolution improvement.
15. Figure 11.15 The mean structural similarity (MSSIM) results for on‐line recover cell images.
Chapter 12
1. Figure 12.1 Smart multimodal CMOS sensor based LOC for personalized diagnosis.